1: learning moderators plate a block.
2: USB power cord a root (from the USB port take electricity, alternative regulated power supply).
3: RS232 serial port extension cord a root.
4:2 a DVD.
1, development tools:
QUARTUS II: select stable version 8.0, and SP1 rc, all function infinite process.
ACTIVE HDL: this is a front end code development environment, support code to write, state machine formation, the principle diagram of the connection, the former simulation and comprehensive simulation and step line simulation, simulation function MODELSIM than more intuitive and simple operation. 7.1 SP2 version, full function unrestricted.
SYPLIFY PRO 9.62: the comprehensive professional tools, a simple but very efficient. Have decryption full function unrestricted.
XHDL: realize VHDL and VERILOG swap. Learning the most fundamental way is to put the unknown things into the known things, if you understand one of the description language, learning another, this tool is first selection. QuanXieMi unrestricted, and I do the video, hand-on teach installation operation and use.
MODELSIM 6.5 se most classic, the most frequently used simulation software. With a complete break.
2, experimental code:
What we write 16 experimental code, based on the VERILOG hardware description language. These code cover the board each peripherals. If the user doing this 16 experiment and master code essentials, FPGA has the introduction.
Here every code though based on peripheral operation, but has a good level modular style, also has the quite strong portability and reusability. Learning from imitation start, so that example is worth you study.
3, hardware schematic diagram, as well as PROTEL format in PCB library.
4, documents and video material. We selected some video data and documentation, let you more concentration of reference and learning.
5, two OC actual project detailed material contains all the source code, a MSP430 processor core applications, one is UART2BUS. The two have video data demonstration, and the need for the PC software.
6, ALTERA official authoritative Chinese tutorial, a total of full set of 40, every 30 minutes, suitable for self-study.
7, DE2 development board official supporting plate.
8, other kinds of tutorial document and application examples.
9, completely decryption X - HDL software, realize VHDL language and language file VERILOG mutual conversion from installation to the actual file conversion have I made video tutorial.
10, VERILOG full Chinese tutorial FLASH. XiaYu smell from beihang university teacher's book extracted essence, total class is not too long, but every example are classic, every sentence explain are in place. From the network, included give you.
11, join southeast university VERILOG handouts, PDF format, each page is four pages PPT lesson plan print, the content and format is a kind of academism story, I believe that the school classmates very familiar with this format, read also must feel very kind and easy to accept?
12, the new added I make 15 minutes of video tutorials, equipped with text, step by step introduce how to use the SIGNAL TAPII grab FPGA internal and external SIGNAL.
Then, in order to more convenient user install USB BLASTER drive, omitting trival directory selection procedure, I made a USB BLASTER drive preinstallation procedures, operation after a time, the user point automatic search can complete driver installation.
14, made detailed installation and decryption of the video, and equipped with text, completely shows from in the CD to MODELSIM 6.5 SE decryption finished can run the entire process, press diagram suo ji, worry about impunity.
15, SYNPLIFY is a very excellent comprehensive software. In the original synplify version 9.62 installation procedures and cracked files based on joined the quickstart manual.